The invention pertains to manufacturing insulated-gate field-effect transistors (MISFETs) for use with very large scale integrated circuits (VLSIs).
In keeping with the latest technological developments, it is possible to manufacture very large scale integrated circuits comprising insulated-gate field-effect transistors, whose channel length (L) amounts to approximately 1 .mu.m as is known, for example, from "IEEE Journal of Solid-State Circuits" Vol. SC-15, No. 4 (August 1980) pp. 417 to 423 and the Annual Report on "Semiconductor Technologies, 1982", published by J. Nishizawa, pp. 280 to 295. In particular, processes are used which have a self-alignment feature.
In such processes the gate electrode including its gate-insulating layer is first produced. The gate insulating layer is used as an implantation mask in the course of the process of implanting the dopings in both the source and the drain region. In the Si-gate described in "Electronics" of Sept. 29, 1960, pp. 88 to 94, a diffusion process similarly employs the gate electrode as a diffusion mask. To obtain a self-alignment of the source contact and of the drain contact with respect to the gate electrode, the latter is etched out of an oxidizable material, particularly out of polycrystalline silicon. Following formation of the contacting windows, a contacting layer is deposited. By employing a photolithographic etching process, the contacts including the conductor leads or also the contacting conductor leads are etched out of the contacting layer.
The procedure of using the gate electrode as a mask in manufacturing the source and the drain region, has disadvantages in the manufacture of integrated insulated-gate field-effect transistors for the use with very large scale integrated circuits. These disadvantages become greater as the channel length becomes smaller. It was found that the relative variations of the channel lengths and accordingly the variations in the spacings of the source regions from the respective neighboring drain regions which occur while etching the gate electrode out of a layer of electrode material due to the unavoidable variations during the under-etching of the masking covering the gate electrode area, become greater as the channel lengths become shorter. Thus the smaller the insulated-gate field-effect transistors are made, the greater the relative variation. When using a thinner layer of electrode material, these variations become smaller. However the sheet resistivity of the electrodes and of lead-in conductors consisting of the electrode material, are increased to an undesirable extent. These problems are not remedied by using the electrode material of conventional types of oxidizable silicides for whose conductivity is by a multiple higher than that of doped polycrystalline silicon.